1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a semiconductor memory device such as a loadless-type CMOS static memory (hereinafter referred to as xe2x80x9cSRAM (Static Random Access Memory)xe2x80x9d) or a loadless-type associative memory (CAM: Content Addressable Memory).
2. Description of the Background Art
FIG. 31 is a view showing the conventional layout configuration of a loadless-type SRAM memory cell formed of four transistors. An equivalent circuit diagram thereof is shown in FIG. 19.
This type of SRAM is shown in, for example, xe2x80x9cA 1.9-um2 Loadless CMOS Four-Transistor SRAM Cell In a 0.18-um Logic Technology,xe2x80x9d in the international academic journal IEDM, pp. 643-646, 1998 or in xe2x80x9cAn Ultrahigh-Density High-Speed Loadless Four-Transistor SRAM Macro with Twisted Bitline Architecture and Triple-Well Shield,xe2x80x9d in the international thesis journal IEEE JSSC, VOL. 36, No. 3, March 2001.
As shown in FIG. 31, a memory cell 1 has four MOS (metal oxide semiconductor) transistors. Concretely, memory cell 1 has NMOS transistors N1, N2 formed in a P well and PMOS transistors P1, P2 formed in an N well.
NMOS transistor N1 is formed in an intersection portion between an N-type diffusion region 2a and a polysilicon interconnection 3c while NMOS transistor N2 is formed in an intersection portion between an N-type diffusion region 2b and a polysilicon interconnection 3b. PMOS transistor P1 is formed in an intersection portion between a P-type diffusion region 2c and a polysilicon interconnection 3a while PMOS transistor P2 is formed in an intersection portion between a P-type diffusion region 2d and a polysilicon interconnection 3a. 
PMOS transistors P1 and P2 are access transistors while NMOS transistors N1 and N2 are driver transistors. Diffusion regions 2a to 2d, respectively, are connected to upper layer wires via contact holes 4a to 4h. 
In the layout configuration shown in FIG. 31, a word line WL is arranged in the lateral direction. Contrarily, a pair of bit lines BL1 and BL2 is arranged in the longitudinal direction. As shown in FIG. 23, the layout configuration of one bit is long in the longitudinal direction and bit lines become long according to such a layout configuration.
As described above, the SRAM memory cell of a four transistor configuration according to the prior art becomes long in the bit line direction and, therefore, the wire capacitance of the bit lines becomes large. In addition, the interval between bit lines BL1 and BL2 becomes narrow so that the capacitance between the bit lines also becomes large. Therefore, there is a problem that the access time is slow.
Furthermore, the direction of the gates and diffusion regions of access transistors P1 and P2 and the direction of the gates and diffusion regions of driver transistors N1 and N2 differ so that the dispersion of the width of the patterns or of the pattern formation positions for forming the gates, and the like, becomes large after photolithographic processing. Therefore, the dispersion of the width or of the formation positions of the gates, and the like, becomes great.
In the case that the dispersion of the gate width, and the like, becomes great, the characteristics of each of the above described transistors fluctuate. In addition, in the case that the formation position of, for example, polysilicon interconnection 3c shifts in the left to right direction in FIG. 23, polysilicon interconnection 3c and contact hole 4a or 4b are short circuited while in the case that the formation position of polysilicon interconnection 3a shifts in the upward to downward direction in FIG. 23, polysilicon interconnection 3a and contact hole 4e to 4g are short circuited. When a gate pattern shifts in any direction, upward, downward, to the left or to the right, there is a possibility that the gate pattern forms a short circuit with a contact hole that is supposed to be isolated and, therefore, there is a problem that it is difficult to secure a margin against dispersion occurring during manufacture due to a mask shift, or the like.
Above described problems may occur not only in a memory cell of a loadless four-transistors type SRAM but also in a memory cell of a loadless four-transistors type CAM.
The present invention is made to solve the above described problems. An object of the present invention is to reduce the wire capacitance of bit lines and the capacitance between bit lines and to secure a margin concerning dispersion in manufacture of a semiconductor memory device such as an SRAM or a CAM.
A semiconductor memory device according to one aspect of the present invention includes: second and third wells of a second conductive type, formed on both sides of a first well of a first conductive type; first and second access MOS transistors of the first conductive type, formed on said second or third well; first and second driver MOS transistors of the second conductive type, formed on said first well; a word line connected to the gates of the first and second access MOS transistors, and extending in the direction along which the first, second and third wells are aligned; and first and second bit lines connected to the sources of the first and second access MOS transistors, respectively, and extending in the direction perpendicular to the direction along which the first, second and third wells are aligned. Then, first and second diffusion regions of the first conductive type for forming the sources/drains of the first and second access MOS transistors and third and fourth diffusion regions of the second conductive type for forming the sources/drains of the first and second driver MOS transistors extend in the same direction, and the gates of the first and second access MOS transistors and the gates of the first and second driver MOS transistors extend in the same direction.
As described above, the first and second bit lines extend in the direction perpendicular to the direction along which the first to third wells are aligned and, thereby, the first and the second bit lines can be made short and the spaces between the bit lines can be made wide. Furthermore, the above described first, second, third and fourth diffusion regions extend in the same direction while the gates of the access MOS transistors and the gates of the driver MOS transistors extend in the same direction and, thereby, the dispersion in the width of the patterns and in the formation positions of the patterns for forming the gates, and the like, can be kept small after photolithographic processing. In addition, in the case that the gates shift in the direction of their extension (longitudinal direction), short circuiting can be avoided between the gates and contact holes that are provided on both sides of the gates in the width direction of the gates.
It is preferable to arrange the first and second access MOS transistors, respectively, on the above described second and third wells. Thereby, the space between the first and second bit lines can be secured widely.
It is preferable to further provide a conductive part for directly connecting the drain of the first access MOS transistor and the drain of the first driver MOS transistor. Example of this conductive part includes a metal wire for directly connecting between contact parts formed on the above described drains or the integration (shared contact) of these contact parts formed of a conductive part filled in into the space over and between the drains.
By providing such a conductive part, the drains can be connected without the intervention of the gates of the driver MOS transistors so that the resistance of the connection between the drains can be reduced.
It is preferable for the gates of the above described first and second access MOS transistors and gates of the first and second driver MOS transistors to extend along a line in the direction perpendicular to the direction in which the first, second and third wells extend. Thereby, dispersion in gate width or in the formation position of the gates can be reduced and, even in the case that the gates shift in the direction of their extension, short circuiting can be avoided between the gates and the contact holes that are provided on both sides of the gates in the width direction of the gates.
A semiconductor memory device according to another aspect of the present invention includes: a first well of a first conductive type; a second well of a second conductive type; first and second access MOS transistors of the first conductive type, formed on the second well; first and second driver MOS transistors of the second conductive type, formed on the first well; a word line connected to the gates of the first and second access MOS transistors extending in the direction along which the first and second wells are aligned; and first and second bit lines that connected to the sources of the first and second access MOS transistors, respectively, and extending in the direction perpendicular to the direction of extension of the word line. Then, first and second diffusion regions of the first conductive type for forming the sources/drains of the first and second access MOS transistors and third and fourth diffusion regions of the second conductive type for forming the sources/drains of the first and second driver MOS transistors extend in the same direction while the gates of the first and second access MOS transistors and the gates of the first and second driver MOS transistors extend in the same direction.
In the case of this aspect also, the first and second bit lines extend in the direction perpendicular to the direction along which the first and second wells are aligned and, therefore, the first and second bit lines can be made short and the intervals between the bit lines can be secured widely. In addition, the first to fourth diffusion regions extend in the same direction while the gates of the access MOS transistors and the gates of the driver MOS transistors extend in the same direction in the same manner as in the first aspect and, therefore, dispersion in the width or the formation position of the gates, or the like, can be made small and a shift of the gates in the longitudinal direction to a certain degree can be allowed.
The above described semiconductor memory device may include: first and second MOS transistors of the second conductive type formed in the above described first well; a word line for read out, connected to gate of the second MOS transistor; and a bit line for read out, connected to the source of the second MOS transistor. In this case, the gate of the first MOS transistor is connected to the gate of the second driver MOS transistor, the drain of the first MOS transistor is set at the ground potential, fifth and sixth diffusion regions of the second conductive type for forming the sources/drains of the first and second MOS transistors and the first, second, third and fourth diffusion regions extend in the same direction and the gates of the first and second MOS transistors, the gates of the first and second access MOS transistors and the gates of the first and second driver MOS transistors extend in the same direction.
The spirit of the second aspect of the present invention can be applied to a two port memory cell that is provided with a port for read out in the above manner. In the case, also, the same effects as in the second aspect can be obtained.
A semiconductor memory device according to still another aspect of the present invention includes: a second well of a second conductive type formed adjacent to a first well of a first conductive type; first and second MOS transistors of the first conductive type formed on the second well; third and fourth MOS transistors of the second conductive type formed on the first well; a word line connected to the gates of the first and second MOS transistors and extending in the direction in which the first and second wells are aligned; and first and second bit lines connected to the sources of the first and second MOS transistors, respectively, and extending in the direction perpendicular to the direction in which the first and second wells are aligned. Then, first and second diffusion regions of the first conductive type for forming the sources/drains of the first and second MOS transistors and third and fourth diffusion regions of the second conductive type for forming the sources/drains of the third and fourth MOS transistors are made to extend in the same direction while the gates of the first and second MOS transistors and the gates of the third and fourth MOS transistors are made to extend in the same direction.
In the case of the present aspect, also, the first and second bit lines can be made short and a wide distance between bit lines can be secured. In addition, the first to fourth diffusion regions and the gates of the first to fourth MOS transistors are made to extend in the same direction, so that the width of patterns for forming the gates or the like after photolithography is carried out and the dispersion of the pattern formation position can be made small.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.